I am a PhD Scholar in the Discipline of Electrical Engineering at nanoDC Lab, IIT Gandhinagar, working with Prof. Nihar Ranjan Mohapatra. I am currently working on designing efficient 2D material interfaces and understanding the coupled effects of dopants, defects, stress, and gate stack in order to handle contact resistance, efficiently design PMOS, and realize a reliable gate stack for WS2 MOSFETs, which can be used in next-generation CMOS technology using Density functional Theory (DFT).

• Detailed CV

Research interests

• 2D materials and devices
• Advanced CMOS Devices
• Advanced materials
• Multiscale modeling

Education

• PhD in Electrical Engineering, IIT Gandhinagar, 2020-present ( Thesis title- Atomistic Interface Engineering of WS2 for Next-Generation CMOS Technology: A First-Principles Investigation)
• B.Tech in Electronics and Telecommunication, NIT Raipur, 2016-2020

Technical skills

EDA Tools - Synopsys Quantum ATK, Synopsys TCAD, Cadence Virtuoso, SPICE, Synopsys dc-shell, Synopsys VCS, Xilinx ISE Design Suite, MATLAB, LT-Spice

Programming - Python3, Verilog, C++, My SQL, LISP, HTML

Relevant courses

⇒ Hetero junctions

⇒ Carrier Transport in Advanced Devices

⇒ Analog CMOS IC design

⇒ Microfabrication

⇒ VLSI Design

⇒ Physics of Transistors

⇒ Microelectronics lab

⇒ Quantum Chemistry

⇒ Electronic Devices and Circuits

⇒ Analog Integrated Circuits

⇒ Digital System Design

⇒ Probability and Stochastic Processes